In order to meet the ever increasing demand for increased device density and performance, a semiconductor technology consisting of a low-k dielectric material (dielectric constant less than silicon dioxide) and an interconnection wiring of copper metallurgy, defined by a double damascene method, is the present day choice for the back end of line (BEOL). Because, dry air has the theoretically lowest dielectric constant of one (1), most low-k materials such as aerogels, hydrogen silsesquioxane (HSQ), fluorinated organic polymers, and organosilicate glass (e.g., SiCOH) are deposited by chemical vapor deposition (CVD). The choice of barrier layers includes tantalum, tungsten and titanium-based alloys.
The high performance interconnection is formed with wirings of high conductivity metallurgies on different levels, insulated from each other with layers of dielectric material and interconnected at desired points. In order to prevent, or to reduce, the corrosive impurity ingression into interconnection wiring structure, at least one layer of the top most layer of interconnection wiring is imbedded in one or more layers of previous standard insulators such as silicon oxide deposited by plasma enhanced chemical vapor deposition (PECVD) using silane (SiH4) or tetraethylorthosilicate (TEOS) precursors. Accordingly, the present day high performance interconnection is comprised of one or more layers of high conductivity copper interconnections, imbedded in the low-k dielectric SiCOH, and bounded on top and bottom by much denser layers of PECVD oxide and BPSG, respectively.
The front end of line (FEOL) corresponds to the levels used to fabricate the transistors, which are composed of silicon from a bulk silicon or silicon-on-insulator (SOI) wafer, high-k dielectric silicon nitride features for electrical insulation and polysilicon gate materials above the transistors in a complementary metal-oxide semiconductor (CMOS) geometry. The corresponding contacts to the source, gate and drain regions of the CMOS transistors often employ a self-aligned silicide (SALICIDE) material, in which a thin metal layer is deposited onto the silicon and annealed to form a metal silicide. Nickel represents the material of choice for current silicide contacts, which possesses a bulk resistivity of approximately 15 to 20 μΩ-cm.
The speed of high-performance semiconductor microcircuitry strongly depends on the overall resistance through the device and interconnect metallization. As the dimensions of the semiconductor features within existing and future generations of microprocessors decrease, the resistance of many of the constituent structures of the semiconductor device increases. For example, the resistance of the vias, which connect the first level of BEOL metallization to the source and drain regions of the transistors (FEOL), is expected to increase as the square of the scaling factor due to electron scattering at small dimensions.
Three major components of the total via (i.e., contact opening) resistance are the bulk resistivity of the via and barrier layer materials, the contact resistance at the bottom via interface and the contact resistance at the top via interface. Current semiconductor manufacturing employs tungsten as the via material and titanium-based barrier layers. Although tungsten possesses a low bulk resistivity (5.5 μΩ-cm), the bulk via resistance is also affected by the presence of voids or seams within the via, a problem that becomes more prevalent as via holes become more difficult to fill using conventional deposition techniques, such as chemical vapor deposition (CVD). However, the contact resistance at the bottom via interface, between the barrier layer and an underlying silicide material formed on top of the source and drain regions, represents an increasing fraction of the total via resistance.
This problem represents a significant impact on the performance and development of semiconductor technology. A method is sought to reduce the effects of contact resistance at the interface between the lowest BEOL via and the underlying silicide layers.
T. Iijima, et al. “A novel selective Ni3Si contact material technique for deep-submicron ULSIs”, 1992 Symposium on VLSI Technology Digest of Technical Papers, IEEE, pages 70-71 discloses a Ni3Si contact material that is said to have a low contact resistance. The Ni3Si contact material is made by first providing a contact opening in a silicon dioxide layer. After providing the contact opening, a TiN/Ti film is deposited. The TiN/Ti film serves as an adhesion/silicidation stop layer. Undoped polySi is then deposited into the contact opening and thereafter a layer of Ni is formed. The Ni silicide contact material is then formed by annealing at 600° C. in argon for one minute. One problem with this prior art approach is that the Ni silicide is formed at a relatively high temperature which may adversely affect the device previously fabricated.
U.S. Pat. No. 5,700,722 to Sumi discloses another approach for forming a silicide contact material. In this prior art approach, a contact opening is first formed in an interlayer insulating layer. A single layer of a Si based material is then deposited, followed by a metal layer. The metal layer consists of Zr, Ni, Pd, Cu, Au, or Ag. After deposition of the metal layer, the structure is heated to a temperature at which the Si based material reacts with the metal to form a silicide material within the contact opening. In the '722 patent, a silicidation temperature of 600° C. is also mentioned.
If view of the above, there is still a need for providing a new material for the contact material as well as method of forming the same. The new material so provided would lower the contact resistance in the contact opening. Additionally, it would also be desirable to provide a method of fabricating a contact material in which the thermal budget used in forming the same is lower than that used in fabricating prior art silicide contact materials.